Static Timing Analysis (STA) / Timing Constraints & Closure Lead

Key Responsibilities

• Develop and maintain complex multi-mode, multi-corner timing constraints (SDC) that are robust and consistent across RTL implementation and signoff environments.
• Ensure high-quality timing constraints using industry-standard validation tools such as Fishtail, GCA, and related methodologies.
• Define and validate timing signoff methodologies, modes, and corner requirements to achieve comprehensive timing coverage.
• Drive pre-route timing analysis, QoR optimization, and timing constraint cleanup to eliminate SDC-related issues and ensure high-quality handoff for STA signoff.
• Utilize strong expertise in SDC development, EDA timing analysis tools, and Tcl scripting within both EDA environments and standalone Linux-based scripting frameworks.
• Own timing closure activities for IPs, subsystems, and/or full-chip designs, ensuring timing convergence across all operating scenarios.
• Lead full-chip interface timing closure, including Design Rule Violation (DRV) analysis and closure.
• Generate and implement timing ECOs using tools such as DMSA, Tweaker, and related optimization utilities.
• Collaborate closely with Architecture, RTL Design, Physical Design, DFT, and Signoff teams to drive successful timing closure and tape-out readiness.
• Mentor junior engineers and contribute to the enhancement of timing methodologies, automation, and signoff practices.

Preferred Qualifications & Experience

• Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related discipline.
• 8+ years of experience in timing constraint development and STA signoff for IP, subsystem, and full-chip designs in both flat and hierarchical implementation flows.
• Strong experience analyzing timing reports and identifying design, synthesis, implementation, and constraint-related timing issues.
• Hands-on experience with industry-standard EDA tools such as Synopsys PrimeTime, Design Compiler, SpyGlass, Fishtail, Tweaker, and related timing signoff tools.
• Proven track record in timing closure of high-performance, high-frequency designs operating in the multi-GHz range.
• Experience driving full-chip STA closure, defining operational modes, corner strategies, and signoff requirements across multiple process-voltage-temperature (PVT) conditions.
• Strong understanding of DFT timing requirements and timing signoff across functional and test modes.
• Good understanding of physical design flows, ECO implementation methodologies, and backend timing optimization techniques.
• Deep knowledge of SDC constraint development and advanced timing analysis methodologies including OCV, AOCV, and POCV.
• Strong Tcl scripting and automation skills are mandatory.
• Excellent communication, problem-solving, and cross-functional collaboration skills with the ability to work effectively in a fast-paced global environment.

Nice to Have

• Experience with automation and methodology development for STA and timing signoff flows.
• Experience supporting advanced technology nodes and complex SoC designs.
• Exposure to low-power design methodologies and timing signoff across multiple power domains.