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Meta's Silicon Engineering team is seeking an ASIC Engineer for low-power design implementation. This role involves driving the physical realization of custom chips from RTL through tapeout, covering synthesis, place-and-route, timing closure, and signoff. You will focus on power modeling, developing EDA tool flows, and applying low-power design techniques for efficient System-on-Chip (SoC) and IP for data center applications. Collaboration with architecture, design, and verification teams is key to delivering high-performance, power-efficient silicon for next-generation infrastructure platforms.
Meta's Silicon Engineering team is building custom silicon solutions that power the infrastructure behind Meta's AI and data center workloads. As an engineer focused on implementation, you may drive the physical realization of complex custom chips from RTL through tapeout, working across synthesis, place-and-route, timing closure, and signoff. In this role, you will work on power modeling for ASICs (architecture to silicon), developing flows around EDA tools, and low-power design to build efficient System on Chip (SoC) and IP for data center applications. You will collaborate with architecture, design, and verification teams to deliver high-performance, power-efficient silicon that meets aggressive PPA targets for Meta's next-generation infrastructure platforms. Responsibilities: Define the power specification at system and module level for Idle, TDP, Typical use cases Develop power modeling infrastructure in Python/C++ Work with or develop architectural simulators in order to model performance and power Build power estimation flows at various levels of abstraction: C-model, RTL, Gate, Layout Apply knowledge of ASIC design processes, including leakage and dynamic power, to evaluate the impact of environment and manufacturing process on power Understand system level concepts and optimize design for low-power Evaluation and Implementation of low-power design techniques at different levels of abstraction Collaborate with RTL designers to identify and resolve timing, area, and power issues early in the design cycle Participate in design reviews and provide implementation feedback to influence upstream architectural and microarchitectural decisions Power characterization on silicon: idle, TDP, use case power; debug power issues on silicon Partner with vendors to drive low-power requirements for SoC interfaces such as LPDDR, PCIe, etc. Partner with EDA tool vendors to select and deploy the appropriate power estimation tools Collaborate with internal HW/SW Co-design, Architecture, Design, DV, and Emulation teams for power flows, optimization and estimation Qualifications: Bachelor's degree in Computer Engineering, Computer Science or Electrical Engineering and/or equivalent practical experience 2+ years of experience with modeling and design with C++ or Python and/or an equivalent high level language Experience with industry-standard EDA tools for synthesis and physical implementation (Synopsys Design Compiler, Cadence Genus, Innovus, or ICC-2) Experience with scripting languages such as Tcl, Python, or Perl for flow automation and data analysis Experience with RTL design using SystemVerilog or other HDL Experience with formal verification or equivalence checking as part of an RTL-to-GDS flow Architecting systems for various design scales (IP blocks, SOC, multi-chip systems) with an understanding of the tradeoffs between performance and power Experience with post-silicon bringup, debugging, and identifying issues across emulator, RTL, and other abstraction levels Familiarity with low-power implementation techniques such as clock gating, multi-voltage domains, and power gating Background in data center or AI accelerator ASIC development Knowledge of front-end and back-end ASIC tools Experience with architectural performance and power models at SoC and system levels Experience managing multiple design releases and working with cross-functional teams to support and debug power issues Ability to communicate clearly with cross-functional internal teams and with vendors Masters degree in Computer Engineering, Computer Science or Electrical Engineering and/or equivalent practical experience