RTL Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE:

As a member of AMD's PCIe Subsystem (PCIeSS) organization, you will join the PCIe IP Enablement (IPE) team as a senior RTL design engineer. You will work closely with the architecture, IP design, physical design, verification, and DFx teams to design and deliver high-quality PCIe subsystem RTL and achieve first-pass silicon success.

THE PERSON:

A successful candidate with RTL design experience, with proven end-to-end ownership of complex digital IP/subsystems from architecture through tape-out. The candidate will be highly accurate and detail-oriented, with strong communication and problem-solving skills, and will help set design development direction and mentor other engineers on the team.

KEY RESPONSIBILITIES:

• Micro-architecture and RTL design for PCIe subsystem blocks
• Develop and maintain RTL for complex digital blocks; author and enforce RTL coding guidelines and design documentation
• Translate architecture requirements into robust, reusable, high-quality RTL
• Drive design reviews and resolve complex RTL debug and correctness issues
• Support subsystem integration and SoC delivery
• Ensure RTL closes cleanly through front-end signoff — Lint, CDC/RDC, synthesis, LEC, STA
• Collaborate with verification, physical design, and architecture teams for seamless design handoff and sign-off

PREFERRED EXPERIENCE:

• Strong RTL design and micro-architecture experience on complex digital IP/subsystems, from RTL to tape-out
• Strong AI knowledge and experience in it's usage to develop skills and agents.
• Direct PCIe protocol and subsystem design experience — a strong plus
• Proficiency with RTL quality flows: Lint, CDC/RDC, synthesis, LEC, and STA
• Experience with Verilog / SystemVerilog RTL design, VCS simulation, and Perl/Shell scripting
• Familiarity with subsystem integration (tile flow, repeaters, SRAM generation, ECO) and DFx awareness (DFT / DFD)
• Excellent problem-solving and debugging skills

ACADEMIC CREDENTIALS:

• Bachelor's or Master's degree in Electrical Engineering / Computer Engineering

LOCATION: Markham & Vancouver

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.