Senior Principal Engineer Analog Design (HBM PHY)

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

As an Analog IC Design Principal Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of a small analog team making a big impact on this organization. Additionally, Marvell has the perfect size and scale for you to learn several aspects of engineering that will be new to you, but also have the time and freedom to dive deep into the details of your specialization on most projects.

What You Can Expect

Senior Principal Analog Lead to drive the design and delivery of next-generation HBM PHY analog and mixed-signal solutions for AI, HPC, and hyperscale systems.

This is a high-impact technical leadership role with ownership of PHY circuit architecture, analog/mixed-signal design, and silicon bring-up, working across digital, system, and packaging domains. You will play a critical role in shaping high-speed interface design at advanced process nodes, pushing the limits of bandwidth, power efficiency, and signal integrity.

Own the analog/mixed-signal architecture of HBM PHY, including:

• TX/RX design, clocking, DLL/PLL, reference circuits
• Training assist circuits, calibration engines, and margining support

Lead design of critical high-speed blocks:

• IO drivers, receivers, equalization, clock distribution, and timing circuits

Define and drive:

• Signal integrity (SI), power integrity (PI), and jitter/noise budgets

Partner closely with logic/RTL architects to co-design:

• Training flows, calibration algorithms, and system behavior

Drive HBM4 implementation to silicon, while influencing next-generation PHY architectures

Collaborate across:

• Physical design, packaging, SI/PI, and system architecture teams

Ensure robust design across:

• Process, voltage, temperature (PVT) corners and variation

Lead design reviews, modeling, and simulation methodologies (including AMS/system-level modeling)

Drive post-silicon bring-up, characterization, and debug for high-speed interfaces

Engage with memory vendors and ecosystem to ensure interface compliance and interoperability

What We're Looking For

Bachelor’s/Master's/PhD in Computer Science, Electrical Engineering or related fields and 15+ years of experience in analog/mixed-signal IC design, with strong focus on high-speed interfaces

Proven track record of delivering silicon-proven PHYs or SerDes at advanced nodes

Deep expertise in:

• High-speed IO design (multi-Gbps range):

  • TX/RX circuits, equalization, clocking, jitter optimization

• Mixed-signal design:

  • DLLs, PLLs, CDR (preferred), voltage references

• Strong understanding of:

  • Signal integrity, power integrity, jitter, noise, and channel effects

  • Package and interconnect impacts (2.5D/3D integration, interposers)
• Experience with:

  • System-level modeling and co-simulation (AMS / behavioral modeling)

• Proven ability to:

  • Drive architecture and design across cross-functional teams

  • Debug complex silicon issues and drive root-cause resolution

Preferred

• Experience with:

  • HBM PHY or memory interfaces (HBM3/HBM4)

• Background in:

  • SerDes, DDR, LPDDR, or GDDR PHY design

• Exposure to:

  • Advanced packaging (2.5D/3D, chiplets, interposers)

• Familiarity with: Equalization techniques, training/DFE concepts, high-speed link design

Prior experience working with Memory vendors and system teams

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity 

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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