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Intel is seeking an Advanced Packaging System Development Integrator to manage critical development silicon at the platform level. This role involves expertise in integrated wafer and package assembly flows, contributing to design risk, planning, and process integration for future product lines. The individual will collaborate with cross-functional teams, drive silicon execution through manufacturing, and communicate project status to stakeholders. Responsibilities include leading technical gap resolution, influencing priorities, owning virtual line activities, and building product/program schedules. The ideal candidate will have strong problem-solving, communication, and collaboration skills.
APTM Advanced Packaging System, Operations and Integration organization is seeking a Development Integrator which will be responsible for managing the execution of critical development silicon at the platform level. These will include Development, Test Vehicle, Engineering and Experimental lots critical to enabling future product lines for Intel's Foundry Customers. The primary role of this individual is to be an expert in the overall wafer and package assembly integrated flows. As well, the individual would have to be familiar with Intel Product Groups Family of products on a design level and provide key contributions to design risk, design planning, and process integration to achieve all key product PADK milestones. In this role, the individual will partner with integration teams, factory organizations (Module and Operations), across single or multiple sites, and will drive execution of critical silicon through all segments of the manufacturing flow to enable on-schedule timelines and milestones. The individual will drive regular lot management meetings with stakeholders, maintain and assess upstream and downstream schedules and communicate accordingly to customers to ensure clear awareness of delays, or ahead of schedule lot arrival.
Responsibilities include:
• Leading teams and driving decisions across any Wafer/Package assembly orgs for key technical gap resolution or technology enablement
• Capable of driving and influencing key stakeholders to drive engineering priorities to meet or beat critical development schedules
• Collaboration with cross-site/functional teams and Intel partners to deliver process requirements on schedule, quality and cost targets
• Virtual Line ownership of baseline material (ENG, TD, DOE). Work weekly build forecast and align starts
• Understanding of manufacturing lines and operations
• Partner with design Integration and wafer/package integration teams
• Understanding of substrate assembly and wafer/package test
• Foundational knowledge of materials and their interactions at a wafer/package level (i.e., Organics/Inorganics, CTE,
• Building product/program level schedules and driving aligned PADK milestones and deliverables to closure
• Understanding and execution of FMEA's
• Understanding of Manufacturing systems and basics of the Mid-Section/Wafer and Package Assembly Flow (including Sort)
The candidate should exhibit the following behavioral traits:
• Strong and pro-active communication
• Demonstration of trust building to technical experts and leverage their skills
• Organizational influence - able to get things done through your network and connections
• High tolerance of ambiguity and demonstrated flexibility and adaptability in fast changing environment
• Demonstrated track record of problem solving with creativity and out-of-box thinking as well as future, strategic, possibility thinking
• Demonstration of strong partnership and interpersonal skills
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
Preferred Qualifications:
• Demonstrated the ability to lead collaborative efforts between Virtual factory sites and Development organizations
• Demonstrated ability to lead and drive activities to successful completion, and mentor others on resolving technical issues.
• Capable of building and maintaining schedules and Gantt timelines in excel or other applications
• Ability to close deliverables in a timely and independent manner
• Understanding of process flows, understanding of key/control parameter importance and determination of minimum technology requirements for tool sharing/back qualification opportunities
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $155,520.00-255,200.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.