Description
Annapurna Labs (our organization within AWS) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.
We are seeking a Sr. Package Layout Engineer to lead the end-to-end physical design of advanced IC packages for next-generation machine learning and data center ASICs.
In this role, you will own the package layout from initial floor planning through tape out and manufacturing release. You'll drive the physical implementation of complex multi-die and advanced packaging architectures, working closely with silicon, SI/PI, thermal, and manufacturing teams to deliver production-ready designs that meet dynamic performance, density, and reliability targets.
Key job responsibilities
- Lead the full package layout cycle from die floor planning, bump/pad assignment, and RDL routing through substrate design, verification, and tape out release.
- Drive physical design of advanced packaging architectures including 2.5D interposer, 3D-IC, fan-out wafer-level packaging, and silicon bridge technologies (e.g., CoWoS, EMIB, or similar).
- Define and optimize package floorplans considering die placement, bump maps, power/ground distribution, high-speed signal escape routing, and decoupling capacitor placement.
- Perform detailed RDL and substrate routing for high-density interconnects including microbumps, C4 bumps, TSVs, microvias, and PTH vias across multi-layer organic substrates and silicon interposers.
- Participate in die-level RDL routing and bump planning in coordination with ASIC physical design teams, ensuring the die-package interface is co-optimized for power delivery and signal routing from the earliest design stages.
- Drive cross-level layout co-optimization across die RDL, interposer/substrate, and PCB levels to achieve the best overall power delivery network and high-speed signaling performance, minimizing impedance discontinuities and routing bottlenecks at each interface boundary.
- Develop and maintain package stack-up definitions in collaboration with SI/PI and materials engineering teams, ensuring impedance targets, layer utilization, and manufacturing constraints are met.
- Create and enforce package design rules and guidelines, working with OSAT partners and foundries to ensure DFM compliance and high yield.
- Run and review physical verification checks (DRC, connectivity, shorts/opens) and drive design closure with zero escapes.
- Manage package design schedules, milestones, and deliverables, coordinating across multiple concurrent projects and tape out cycles.
- Collaborate with SI/PI engineers to incorporate electrical constraints into the physical layout — impedance-controlled routing, power plane optimization, and critical net shielding.
- Interface with OSAT vendors and foundry partners on substrate and interposer manufacturing feasibility, design rule negotiations, and process capability alignment.
- Identify packaging technology risks early and propose design or process mitigations to ensure reliability and manufacturability.
- Mentor junior layout engineers and contribute to the development of team best practices, automation flows, and design reuse strategies.
About the team
Our team is dedicated to supporting new members. We have a broad mix of experience levels and tenures, and we’re building an environment that celebrates knowledge-sharing and mentorship. Our senior members enjoy one-on-one mentoring and thorough, but kind, code reviews. We care about your career growth and strive to assign projects that help our team members develop your engineering expertise so you feel empowered to take on more complex tasks in the future.
